1. Field of the Invention
The present invention relates to memory device and, more particularly, to a novel structure of chalcogenide memory and a method of manufacturing the same.
2. Description of the Prior Art
A conventional chalcogenide memory structure is shown in FIG. 1 (Prior Art). In FIG. 1, a N+ doping layer 12 is formed on the substrate 10. A N− doping layer 14 is formed on the N+ doping layer 12. A N+ doped region 16 formed in the N− doping layer 14. A P+ doped region 18 is formed in the N− doping layer 14. A dielectric layer 20 is formed on the substrate generally consisting of a SiO2 layer. A contact plug 22 includes a barrier layer 24 and a metal layer 26. An electrode is formed on contact plug 22, wherein the electrode 28 includes a lower electrode 30, a chalcogenide layer 32 and an upper electrode 34.
However, this structure has some essential disadvantages. Since thickness and doping concentration of the N− doping layer and the N+ doping layer are not easily controlled, a breakdown voltage (BDV) can not be adjusted. In addition, since there is no isolation, P+/P+ punch and WL/WL (word line) punch easily occur. Thus, the minimization of the feature size can not be achieved.